2024, Vol. 5, Issue 1, Part A
Design and optimization of low-power CMOS-based D-type flip-flops for high-speed digital circuits
Author(s): Jun Bai and Xue Xia
Abstract: This article reviews the latest advancements and methodologies in designing low-power CMOS-based D-type flip-flops, crucial for high-speed digital circuits. With the exponential growth in digital applications requiring efficient power management and high performance, optimizing flip-flop designs has become imperative. This review synthesizes current research findings, highlights design challenges, and discusses potential future advancements in flip-flop technology.
Pages: 20-22 | Views: 460 | Downloads: 133
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How to cite this article:
Jun Bai, Xue Xia. Design and optimization of low-power CMOS-based D-type flip-flops for high-speed digital circuits. Int J Electr Data Commun 2024;5(1):20-22.
